(1) Field of the Invention
The invention relates to a parameter extraction method for semiconductor devices, and especially relates to a parameter extraction method for accurate determination of effective channel width in MOSFETs to fabricated in nano-scale technology.
(2) Description of the Prior Art
With the advancement of the electronic products, the size of the components in the electronic products continuously pursues the miniaturization to nano-scale dimensions. The electronic products emphasize the appeals, such as multi functions, small size, and light weight, so as to increase the functions of the integrated circuits and to minimize the size of the integrated circuits, for improving the performance.
With increasing the functions of the integrated circuits and minimizing the size of the integrated circuits, the isolation of internal components must be enhanced to avoid the impact of the internal components, such as contacting each other. Therefore, the shallow trench isolation (STI) technique has been widely used since 0.25 μm technology node and presently continued to nano-scale nodes. However, the original STI technique generally suffered current and field crowding, and even worse gate leakage near the top corner, due to sharp corner profile and poor formation of the gate oxide. Therefore, the top corner rounding becomes a key technique in STI process for solving the above problems. However, the top corner rounding (TCR) technique generally leads to an extension of the active region near the trench edge and the resulted increase of the effective channel width, namely delta channel width (ΔW). The influence of the delta channel width becomes significant in narrow width devices, particularly for the multi-finger MOSFETs with aggressively scaled finger or channel width. The impact of delta width effect can be measured from current-voltage (I-V) characteristics, capacitance-voltage (C-V) characteristics, and high-frequency characteristics, etc. Therefore, the precise extraction of the effective channel width for miniaturized devices becomes indispensable for accurate characterization and modeling, which is particularly important for radio frequency (RF) and analog device and circuit design.
The conventional method for the delta channel width extraction is based on I-V characteristics, such as drain current (Ids) and transconductance (Gm) measured from the MOSFETs with different channel widths. Both Ids and Gm are a function of the effective mobility (μeff) and the effective channel width (Weff), which are critically dependent on the channel width, due to the STI stress and top corner rounding (TCR) induced delta channel width, respectively. However, said conventional method requires simultaneous best fitting to both μeff and Gm in which μeff has to be known before the extraction of the delta channel width. The mentioned process introduces errors in the initially extracted μeff, without consideration of the delta channel width. Therefore, multiple steps of iteration is required to update μeff with the previously extracted delta channel width and then to re-extract the delta channel width from the best fitting to the updated μeff and Gm. The second problem with this I-V based method is that a very wide MOSFET is needed to act as the reference device in which the influence from the STI stress and the delta channel width becomes extremely small and can be neglected. The last problem is related to the short channel devices in which the source/drain parasitic resistances (RDS,ext) may dominate the channel resistance and have to be extracted and eliminated for accurate determination of μeff. The deviation of the extracted RDS,ext will introduce additional errors in the extracted μeff and then the delta channel width.
Consequently, a new method, which can solve the mentioned problems with conventional method and then ensure accurate extraction of to the delta channel width and the effective channel width of the semiconductor devices becomes the major objective of the invention.